Microelectronic elements such as semiconductor chips commonly are provided with elements which protect the microelectronic element and facilitate its connection to other elements of a larger circuit. For example, a semiconductor chip typically is provided as a small, flat element having oppositely facing front and rear surfaces and contacts at the front surface. The contacts are electrically connected to the numerous electronic circuit elements formed integrally within the chip. Such a chip most commonly is provided in a package having a miniature circuit panel referred to as a substrate. The chip is typically mounted to the substrate with the front or rear surface overlying a surface of the substrate, and the substrate typically has terminals at a surface of the substrate. The terminals are electrically connected to the contacts of the chip. The package typically also includes some form of covering overlying the chip on the side of the chip opposite from the substrate. The covering serves to protect the chip and, in some cases, the connections between the chip and the conductive elements of the substrate. Such a packaged chip may be mounted to a circuit panel, such as a circuit board, by connecting the terminals of the substrate to conductive elements such as contact pads on the larger circuit panel.
In certain packages, the chip is mounted with its front surface overlying an upper surface of the substrate, whereas terminals are provided on the oppositely facing lower surface. A mass of a dielectric material overlies the chip and, most typically, the electrical connections between the chip and the conductive elements of the substrate. The dielectric mass may be formed by molding a flowable dielectric composition around the chip so that the dielectric composition covers the chip and all or part of the top surface of the substrate. Such a package is commonly referred to as an “overmolded” package, and the mass of dielectric material is referred to as the “overmold.” Overmolded packages are economical to manufacture and thus are widely used.
In some applications, it is desirable to mount a plurality of chips 12 overlying an upper surface 14 of a substrate 16 in a face down orientation, such as in a quad face down (QFD) or like orientation as shown in FIG. 1. See, for example, U.S. Pat. No. 8,338,963 issued Oct. 25, 2012 and U.S. Publication No. 2013/0015591 published Jan. 17, 2013, the disclosures of which are incorporated by reference herein. The chips 12 may be attached to the surface 14 by an attachment layer 18, with contacts 22 at the front faces of the chips 12 overlying openings 20 in the substrate 16. The openings 20 have an elongated dimension, extend to the front face of the chip and have portions 24 at opposite ends of the elongated dimension through which dielectric material may flow from an opening in the attachment layer 18 during manufacture of the microelectronic package. In microelectronic packages having chips in QFD and like orientations as shown in FIG. 1, the openings typically are not arranged so the elongated dimension of the openings extends in a same longitudinal direction, as is customary when chips are arranged in a single or dual face down orientation in a microelectronic package. During manufacture of such packages, when encapsulant material is provided to encapsulate the elements of the package, which includes filling the openings with the encapsulant material, the material is typically flowed from a molding tool 30 in a single direction X over the top surface or attachment layer 18 side of the substrate 16. In QFD or like orientations, the openings 20 that extend in a longitudinal direction transverse, such as perpendicular, to the encapsulant material flow direction X may not become completely filled by the encapsulant material, because voids at which air is entrapped may form within the openings, which is undesirable.
Despite the considerable effort devoted in the art to development of microelectronic packages having multiple electronic elements, further improvement would be desirable.